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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview Presettable Counters MC54/74HC160A MC54/74HC162A High-Performance Silicon-Gate CMOS The MC54/74HC160A and HC162A are identical in pinout to the LS160 and LS162, respectively. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC160A and HC162A are programmable BCD counters with asynchronous and synchronous Reset inputs, respectively. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 234 FETs or 58.5 Equivalent Gates 16 1 J SUFFIX CERAMIC PACKAGE CASE 620-10 16 1 N SUFFIX PLASTIC PACKAGE CASE 648-08 16 1 D SUFFIX SOIC PACKAGE CASE 751B-05 ORDERING INFORMATION LOGIC DIAGRAM MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD 14 13 12 11 Q0 Q1 Q2 Q3 CLOCK RIPPLE CARRY OUT P0 P1 P2 P3 BCD OUTPUTS Ceramic Plastic SOIC P0 PRESENT DATA INPUTS P1 P2 P3 3 4 5 6 PIN ASSIGNMENT RESET 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RIPPLE CARRY OUT Q0 Q1 Q2 Q3 ENABLE T LOAD CLOCK 2 15 RESET LOAD COUNT ENABLES ENABLE P ENABLE T PIN 16 = VCC PIN 8 = GND ENABLE P GND FUNCTION TABLE Inputs Clock Reset* L H H H H Load X L H H H Enable P X X H L X Enable T X X H X L Output Q Reset Load Preset Data Count No Count No Count This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 9/96 (c) Motorola, Inc. 1996 II I IIIIIIIIIII II I I II I I IIIIIIIIIII IIIIIII IIIIIIIIIII IIIIIIIIIII IIII I III I II IIIIIIIIIII IIIIIII Device HC160 HC162 Count Mode BCD BCD Reset Mode Asynchronous Synchronous 1 * HC162A only. HC160A is an Asynchronous Reset Device H = high level L = low level X = don't care REV 0 MC54/74HC160A MC54/74HC162A IIIIIIII I I I I IIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII III III I I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package mW TstgIIIIIIIIIIIIII - 65 to + 150 Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) 260 300 _C _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). III I I III I IIIIIIIIIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I II IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC - 55 0 0 0 + 125 1000 500 400 RECOMMENDED OPERATING CONDITIONS _C ns tr, tf VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MOTOROLA 2 High-Speed CMOS Logic Data DL129 -- Rev 6 II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I I II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I II I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I II I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol S bl VOH VOL ICC VIH VIL Iin Maximum Quiescent Supply Current (per Package) Maximum Input Leakage Current Maximum Low-Level Output Voltage Minimum High-Level Output Voltage Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter P Vin = VCC or GND Iout = 0 A Vin = VCC or GND Vin = VIH or VIL Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL Vin = VIH or VIL |Iout| 20 A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A v v v v Test C di i T Conditions |Iout| 2.4 m |Iout| 4.0 mA |Iout| 5.2 mA |Iout| 2.4 m |Iout| 4.0 mA |Iout| 5.2 mA 3 v v v v v v VCC V 6.0 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 MC54/74HC160A MC54/74HC162A - 55 to 25_C 0.1 0.26 0.26 0.26 2.48 3.98 5.48 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.1 0.1 0.1 1.9 4.4 5.9 4 Guaranteed Limit v 85_C v 125_C 1.0 0.33 0.33 0.33 2.34 3.84 5.34 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.1 0.1 0.1 1.9 4.4 5.9 40 1.0 0.40 0.40 0.40 2.20 3.70 5.20 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 160 0.1 0.1 0.1 1.9 4.4 5.9 MOTOROLA Unit Ui A A V V V V MC54/74HC160A MC54/74HC162A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I III I I I I I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I III I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I Guaranteed Limit Symbol S bl fmax Parameter P VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -- - 55 to 25_C 6.0 TBD 30 35 v 85_C v 125_C 4.8 TBD 24 28 4.0 TBD 20 24 Unit Ui Maximum Clock Frequency (50% Duty Cycle)* (Figures 1 and 7) MHz tPLH Maximum Propagation Delay, Clock to Q (Figures 1 and 7) 170 TBD 34 29 205 TBD 41 35 210 TBD 42 36 160 TBD 32 27 195 TBD 39 33 175 TBD 35 30 215 TBD 43 37 220 TBD 44 37 75 27 15 13 10 215 TBD 43 37 255 TBD 51 43 265 TBD 53 45 200 TBD 40 34 245 TBD 49 42 220 TBD 44 37 270 TBD 54 46 275 TBD 55 47 95 32 19 16 10 255 TBD 51 43 310 TBD 62 53 315 TBD 63 54 240 TBD 48 41 295 TBD 59 50 265 TBD 53 45 325 TBD 65 55 330 TBD 66 56 110 36 22 19 10 ns tPHL tPHL Maximum Propagation Delay, Reset to Q (HC160A Only) (Figures 2 and 7) ns tPLH Maximum Propagation Delay, Enable T to Ripple Carry Out (Figures 3 and 7) ns tPHL tPLH Maximum Propagation Delay, Clock to Ripple Carry Out (Figures 1 and 7) ns tPHL tPHL Maximum Propagation Delay, Reset to Ripple Carry Out (HC160A Only) (Figures 2 and 7) Maximum Output Transition Time, Any Output (Figures 1 and 7) ns tTLH, tTHL ns Cin Maximum Input Capacitance pF * Applies to noncascaded/nonsynchronously clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine f max. However, if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the f max in the table above is applicable. See Applications Information in this data sheet. NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Di i i C P Dissipation Capacitance (P P k i (Per Package)* )* 60 pF F * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). MOTOROLA 4 High-Speed CMOS Logic Data DL129 -- Rev 6 III I I I I I IIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I III I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). High-Speed CMOS Logic Data DL129 -- Rev 6 TIMING REQUIREMENTS (Input tr = tf = 6 ns) Symbol S bl trec trec tr, tf tsu tsu tsu tsu tw tw th th th th Maximum Input Rise and Fall Times (Figure 1) Minimum Pulse Width, Reset (HC160A only) (Figure 2) Minimum Pulse Width, Clock (Figure 1) Minimum Recovery Time, Load Inactive to Clock (Figure 5) Minimum Recovery Time, Reset Inactive to Clock (HC160A only) (Figure 2) Minimum Hold Time, Clock to Enable T or Enable P (Figure 6) Minimum Hold Time, Clock to Reset (HC162A only) (Figure 4) Minimum Hold Time, Clock to Load (Figure 5) Minimum Hold Time, Clock to Preset Data Inputs (Figure 5) Minimum Setup Time, Enable T or Enable P to Clock (Figure 6) Minimum Setup Time, Reset to Clock (HC162A only) (Figure 4) Minimum Setup Time, Load to Clock (Figure 5) Minimum Setup Time, Preset Data Inputs to Clock (Figure 5) Parameter P 5 VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C 1000 800 500 400 3 TBD 3 3 3 TBD 3 3 3 TBD 3 3 125 TBD 25 21 125 TBD 25 21 200 TBD 40 34 160 TBD 32 27 135 TBD 27 23 150 TBD 30 26 80 TBD 16 14 80 TBD 16 14 50 TBD 10 9 Guaranteed Limit 1000 800 500 400 3 TBD 3 3 3 TBD 3 3 3 TBD 3 3 100 TBD 20 17 100 TBD 20 17 155 TBD 31 26 155 TBD 31 26 250 TBD 50 43 200 TBD 40 34 170 TBD 34 29 190 TBD 38 33 65 TBD 13 11 1000 800 500 400 3 TBD 3 3 3 TBD 3 3 3 TBD 3 3 120 TBD 24 20 120 TBD 24 20 190 TBD 38 32 190 TBD 38 32 300 TBD 60 51 240 TBD 48 41 205 TBD 41 35 225 TBD 45 38 75 TBD 15 13 MC54/74HC160A MC54/74HC162A v 85_C v 125_C MOTOROLA Unit Ui ns ns ns ns ns ns ns ns ns ns ns ns ns MC54/74HC160A MC54/74HC162A FUNCTION DESCRIPTION The HC160A/162A are programmable 4-bit synchronous counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading, and count- enable controls. The HC160A and HC162A are BCD counters with asynchronous Reset, and synchronous Reset, respectively. INPUTS Clock (Pin 2) The internal flip-flops toggle and the output count advances with the rising edge of the Clock input. In addition, control functions, such as resetting (HC162A) and loading occur with the rising edge of the Clock input. Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6) These are the data inputs for programmable counting. Data on these pins may be synchronously loaded into the internal flip-flops and appear at the counter outputs. P0 (pin 3) is the least-significant bit and P3 (pin 6) is the most-significant bit. OUTPUTS Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11) These are the counter outputs (BCD or binary). Q0 (pin 14) is the least-significant bit and Q3 (pin 11) is the most-significant bit. Ripple Carry Out (Pin 15) When the counter is in its maximum state (1001 for the BCD counters or 1111 for the binary counters), this output goes high, providing an external look-ahead carry pulse that may be used to enable successive cascaded counters. Ripple Carry Out remains high only during the maximum count state. The logic equation for this output is: Ripple Carry Out = Enable T Q0 Q1 Q2 Q3 for BCD counters HC160A and HC162A Load H L X X CONTROL FUNCTIONS Resetting A low level on the Reset pin (pin 1) resets the internal flip- flops and sets the outputs (Q0 through Q3) to a low level. The HC160A resets asynchronously and the HC162A resets with the rising edge of the Clock input (synchronous reset). Loading With the rising edge of the Clock, a low level on Load (pin 9) loads the data from the Preset Data Input pins (P0, P1, P2, P3) into the internal flip-flops and onto the output pins, Q0 through Q3. The count function is disabled as long as Load is low. Although the HC160A and HC162A are BCD counters, they may be programmed to any state. If they are loaded with a state disallowed in BCD code, they will return to their normal count sequence within two clock pulses (see the Output State Diagram). Count Enable/Disable These devices have two count-enable control pins: Enable P (pin 7) and Enable T (pin 10). The devices count when these two pins and the Load pin are high. The logic equation is: Count Enable = Enable P Enable T Load The count is either enabled or disabled by the control inputs according to Table 1. In general, Enable P is a count- enable control; Enable T is both a count-enable and a Ripple-Carry Output control. Table 1. Count Enable/Disable Control Inputs Enable P H H L X Enable T H H H L Result at Outputs Q0 - Q3 Count No Count No Count No Count Ripple Carry Out High when Q0 - Q3 g are maximum* High when Q0 - Q3 are maximum* L * Q0 through Q3 are maximum for the HC160A and HC162A when Q3 Q2 Q1 Q0 = 1001. OUTPUT STATE DIAGRAMS HC160A and HC162A BCD Counters 0 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 MOTOROLA 6 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC160A MC54/74HC162A SWITCHING WAVEFORMS tr 90% 50% 10% tw 1/fmax tPLH tPHL ANY OUTPUT 90% 50% 10% tTLH tTHL ANY OUTPUT tf VCC GND RESET tPHL 50% trec VCC CLOCK 50% GND 50% GND tw VCC CLOCK Figure 1. tr ENABLE T 90% 50% 10% tPLH 90% 50% 10% tTLH tf VCC GND tPHL CLOCK tTHL tsu RESET 50% Figure 2. th VCC 50% GND RIPPLE CARRY OUT Figure 3. Figure 4. HC162A Only VALID INPUTS P0, P1, P2, P3 VCC 50% GND tsu LOAD 50% GND tsu CLOCK th 50% GND trec VCC th VCC ENABLE T OR ENABLE P 50% GND tsu CLOCK th VCC 50% GND VALID VCC Figure 5. TEST CIRCUIT TEST POINT OUTPUT DEVICE UNDER TEST CL* Figure 6. * Includes all probe and jig capacitance Figure 7. High-Speed CMOS Logic Data DL129 -- Rev 6 7 MOTOROLA MOTOROLA MC54HC160A * MC74HC160A BCD Counter with Asynchronous Reset Q0 14 Q0 P0 3 T0 R C C LOAD LOAD P0 Q0 Q1 13 Q1 MC54/74HC160A MC54/74HC162A P1 4 T1 R C C LOAD LOAD P1 Q1 Q2 12 Q2 P2 5 T2 R C C LOAD LOAD P2 Q2 8 T3 R C C LOAD LOAD P3 R C C LOAD LOAD Q3 11 Q3 P3 6 Q3 15 RIPPLE CARRY OUT ENABLE P 7 ENABLE T 10 VCC = PIN 16 GND = PIN 8 RESET 1 CLOCK 2 High-Speed CMOS Logic Data DL129 -- Rev 6 LOAD 3 The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle- Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low. MC54/74HC160A MC54/74HC162A HC160A, HC162A TIMING DIAGRAM Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to BCD seven. 3. Count to eight, nine, zero, one, two, and three. 4. Inhibit. RESET (HC160A) RESET (HC162A) LOAD (ASYNCHRONOUS) (SYNCHRONOUS) P0 PRESET DATA INPUTS P1 P2 P3 CLOCK (HC160A) CLOCK (HC162A) ENABLE P ENABLE T Q0 Q1 OUTPUTS Q2 Q3 RIPPLE CARRY OUT RESET COUNT ENABLES 7 LOAD 8 9 0 1 2 3 INHIBIT COUNT High-Speed CMOS Logic Data DL129 -- Rev 6 9 MOTOROLA MOTOROLA MC54HC160A * MC74HC160A BCD Counter with Synchronous Reset 14 Q0 Q0 P0 3 T0 R C C LOAD LOAD P0 Q0 Q1 13 Q1 MC54/74HC160A MC54/74HC162A P1 4 T1 R C C LOAD LOAD P1 Q1 Q2 12 Q2 10 T3 R C C LOAD LOAD P3 R C C LOAD LOAD P2 5 T2 R C C LOAD LOAD P2 Q2 Q3 11 Q3 P3 6 Q3 15 RIPPLE CARRY OUT ENABLE P 7 ENABLE T 10 VCC = PIN 16 GND = PIN 8 RESET 1 CLOCK 2 High-Speed CMOS Logic Data DL129 -- Rev 6 LOAD 3 The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle- Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low. MC54/74HC160A MC54/74HC162A TYPICAL APPLICATIONS CASCADING N-Bit Synchronous Counters LOAD INPUTS INPUTS INPUTS LOAD H = COUNT L = DISABLE H = COUNT L = DISABLE P0 P1 P2 P3 LOAD P0 P1 P2 P3 LOAD P0 P1 P2 P3 ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT TO MORE SIGNIFICANT STAGES RESET OUTPUTS CLOCK NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and Clock. OUTPUTS OUTPUTS Nibble Ripple Counter INPUTS LOAD ENABLE P ENABLE T LOAD P0 P1 P2 P3 LOAD INPUTS INPUTS P0 P1 P2 P3 LOAD P0 P1 P2 P3 ENABLE P ENABLE T CLOCK CLOCK R RESET Q0 Q1 Q2 Q3 RIPPLE CARRY OUT ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT ENABLE P ENABLE T CLOCK R Q0 Q1 Q2 Q3 RIPPLE CARRY OUT TO MORE SIGNIFICANT STAGES OUTPUTS OUTPUTS OUTPUTS High-Speed CMOS Logic Data DL129 -- Rev 6 11 MOTOROLA MC54/74HC160A MC54/74HC162A TYPICAL APPLICATION HC162A OTHER INPUTS Q0 Q1 Q2 Q3 RESET OPTIONAL BUFFER FOR NOISE REJECTION OUTPUT Modulo-5 Counter The HC162A facilitates designing counters of any modulus with minimal external logic. The output is glitch-free due to the synchronous Reset. MOTOROLA 12 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC160A MC54/74HC162A OUTLINE DIMENSIONS -A - 16 9 J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V -B - C L 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51 -T SEATING - PLANE N E F G D 16 PL 0.25 (0.010) M K M J 16 PL 0.25 (0.010) M TB S TA S DIM A B C D E F G J K L M N -A - 16 9 N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R B 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 0.250 0.270 6.35 6.85 0.145 0.175 3.69 4.44 0.015 0.021 0.39 0.53 0.040 0.070 1.77 1.02 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.008 0.015 0.21 0.38 0.110 0.130 2.80 3.30 0.295 0.305 7.50 7.74 0 10 0 10 0.020 0.040 0.51 1.01 F S C L -T - H G D 16 PL 0.25 (0.010) M SEATING PLANE K J TA M M -A - 16 9 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -B - 1 8 P 8 PL 0.25 (0.010) M B M G F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 K C -T SEATING - PLANE R X 45 M D 16 PL 0.25 (0.010) M J T B S A S High-Speed CMOS Logic Data DL129 -- Rev 6 13 MOTOROLA MC54/74HC160A MC54/74HC162A Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA 14 *MC74HC160A/D* MC74HC160A/D High-Speed CMOS Logic Data DL129 -- Rev 6 |
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